module alu (
        input [31:0] data_a,
        input [31:0] data_b,

        input [3:0] opcode,

        output reg [31:0] alu_result,
        output overflow, zero

    );
    wire signed [31:0] data_a_signed = data_a;
    wire signed [31:0] data_b_signed = data_b;

    assign overflow = 1'b0;
    assign zero = data_a_signed == data_b_signed;

    always @ (*) begin
        case (opcode)
            4'b0000:
                alu_result = data_a + data_b;
            4'b0001:
                alu_result = data_a - data_b;
            4'b0010:
                alu_result = (data_a_signed < data_b_signed )? 1: 0;
            4'b0011:
                alu_result = (data_a < data_b )? 1: 0;
            4'b0100:
                alu_result = data_a ^ data_b;
            4'b0101:
                alu_result = data_a << data_b;
            4'b0110:
                alu_result = data_a | data_b;
            4'b0111:
                alu_result = data_a & data_b;
            4'b1000:
                alu_result = (data_a_signed < data_b_signed )? 1: 0;
            4'b1001:
                alu_result = (data_a < data_b )? 1: 0;
             4'b1111:
                alu_result = data_b;   
            default:
                alu_result = 'b0;
        endcase
    end

endmodule
